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(c) 2014. renesas electronics corporation. all rights reserved. page 1 of 13 date: feb. 6, 2014 renesas technical update 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan renesas electronics corporation product category mpu/mcu document no. tn-rl*-a 023a/e rev. 1 .00 title correction for incorrect description notice rl78/g10 descriptions in the hardware user?s manual rev. 1.00 changed information category technical notification applicable product rl78/g10 r5f10yxxx lot no. reference document rl78/g10 user?s manual: hardware rev.1.00 r01uh0384ej0100 (jun. 2013) all lots this document describes misstatements found in the rl78 /g10 user?s manual: hardware rev.1.00 (r01uh0384ej0100). corrections applicable item applicable page contents flash rom: 4 kb of 10-pin products, and 16-pin products page 7 specifications added 3. 1 address space pages 22 to 24 incorrect descriptions revised 6. 3. 5 timer channel enable status register 0 (te0, teh0 (8-bit mode)) page 121 incorrect descriptions revised 6. 3. 8 timer output enable register 0 (toe 0) page 124 incorrect descriptions revised 6. 4. 2 basic rules of 8-bit timer operation function (only channels 1 and 3) page 132 specifications added figure 10-13. conversion oper ation of a/d converter page 235 incorrect descriptions revised 10. 9. 3 conflicting operations page 242 descriptions added 24. 3. 1 pin characteristics p age 556 specifications extended 24. 6. 1 a/d converter characterist ics page 567 specifications added 24. 6. 4 data retention power supply voltage characteristics page 568 descriptions added document improvement the above corrections will be made for the next revision of the user?s manual: hardware.
renesas technical update tn-rl*-a023a/e date: feb. 6 , 2014 (c) 2014. renesas electronics corporation. all rights reserved. page 2 of 13 corrections in the user?s manual: hardware no. corrections and applicable items pages in this document for corrections document no. english r01uh0384ej0100 1 flash rom: 4 kb of 10-pin products, and 16-pin products page 7 page 3 2 3. 1 address space pages 22 to 24 pages 4 to 6 3 6. 3. 5 timer channel enable status register 0 (te0, teh0 (8-bit mode)) page 121 page 7 4 6. 3. 8 timer output enable re gister 0 (toe0) page 124 page 7 5 6. 4. 2 basic rules of 8-bit timer operation function (only channels 1 and 3) page 132 page 7 6 figure 10-13. conversi on operation of a/d converter page 235 page 8 7 10. 9. 3 conflicting op erations page 242 page 9 8 24. 3. 1 pin characteristics page 556 page 10 9 24. 6. 1 a/d converter characte ristics page 567 pages 11 and 12 10 24. 6. 4 data retention power supply voltage characteristics page 568 page 13 incorrect: bold with underline ; correct: gray hatched revision history rl78/g10 user?s manual: hardware rev.1.00 correction for incorrect description notice document number date description tn-rl*-a a/e )he. , 2014 ) irst edition issued no.1 to 10 in corrections (this notice)
renesas technical update tn-rl*-a 023 a/e 'ate: )he. , 201 (c) 2014. renesas electronics corporation. all rights reserved. page 3 of 13 1. flash rom: 4 kb of 10-pin products, and 16-pin products (page 7) flash rom: 4 kb of 10-pin products and 16-pin products will be added to line-up in the group of rl78/g10. the details of functions of 16-pi n products will be made for the next revision of the user?s manual: hardware. this outline describes the function at the time when pe ripheral i/o redirection regist er (pior) is set to 00h. item 10-pin 16-pin r5f10y14asp r5f10y16asp r5f10y17asp r5f10y44asp r5f10y46asp r5f10y47asp code flash memory 1 kb 2 kb 4 kb 1 kb 2 kb 4 kb ram 128 b 256 b 512 b 128 b 256 b 512 b main system clock high-speed system clock ? x1, x2 (crystal/ceramic) oscillation, external main system clock input (exclk): 1 to 20 mhz: v dd = 2.7 to 5.5 v 1 to 5 mhz: v dd = 2.0 to 5.5 v note 3 high-speed on-chip oscillator clock ? 1.25 to 20 mhz (v dd = 2.7 to 5.5 v) ? 1.25 to 5 mhz (v dd = 2.0 to 5.5 v note 3 ) low-speed on-chip oscillator clock 15 khz (typ) general-purpose register 8-bit register ? 8 minimum instruction execution time 0.05 ? s (20 mhz operation) instruction set ? data transfer (8 bits) ? adder and subtractor/logical operation (8 bits) ? multiplication (8 bits ? 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 8 14 cmos i/o 6 (n-ch open-drain output (v dd tolerance): 2) 10 (n-ch open-drain output (v dd tolerance): 4) cmos input 2 4 timer 16-bit timer 2 channels 4 channels watchdog timer 1 channel 12-bit interval timer ? 1 channel timer output 2 channels (pwm output: 1) 4 channels (pwm outputs: 3 note 1 ) clock output/buzzer output 1 2.44 khz to 10 mhz: (peripheral hardware clock: f main = 20 mhz operation) comparator ? 1 8-/10-bit resolution a/d converter 4 channels 7 channels serial interface [10-pin prod ucts] csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [16-pin products] csi: 2 channels/simplified i 2 c: 1 channel/uart: 1 channel i 2 c bus ? 1 channel vectored interrupt sources internal 8 14 external 3 5 key interrupt 6 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by selectable power-on-reset ? internal reset by illegal instruction execution note 2 ? internal reset by data retention lower limit voltage selectable power-on-reset circuit ? detection voltage rising edge (v spor ): 2.25 v/2.68 v/3.02 v/4.45 v (max.) falling edge (v spdr ): 2.20 v/2.62 v/2.96 v/4.37 v (max.) on-chip debug function provided power supply voltage v dd = 2.0 to 5.5 v note 3 operating ambient temperature t a = - 40 to + 85 ? c notes 1. the number of outputs varies, depending on the setting of channels in use and the num ber of the master (see 6.9.4 operation as multiple pwm output function ). 2. the illegal instruction is generated when instruction co de ffh is executed. reset by the illegal instruction execution not issued by emulation with the on-chip debug emulator. 3. use this product within the voltage range fr om 2.25 to 5.5 v because the detection voltage (v spor ) of the selectable power-on-reset (spor) circuit should also be considered.
renesas technical update tn-rl*-a023a/e date: feb. 6,201 4 (c) 2014. renesas electronics corporation. all rights reserved. page 4 of 13 2. 3. 1 address space (pages 22 to 24) incorrect: correct:
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 5 of 13 incorrect: correct:
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 6 of 13 incorrect: correct:
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 7 of 13 3. 6. 3. 5 timer channel enable status register 0 (te0, teh0 (8-bit mode)) (page 121) incorrect: the te0 and teh0 registers are used to enable or stop the timer operation of each channel. each bit of the te0 and teh0 registers corresp ond to each bit of the timer channel start register 0 (ts0, tsh0) and the timer channel stop register 0 (tt0, tth0). when a bit of the ts0 and tsh0 registers is set to 1, the correspon ding bit of te0 and teh0 is set to 1. when a bit of the tt0 and tth0 registers is set to 1, the corresponding bit of te0 and teh0 is cleared to 0. the te0 and teh0 registers can be read by an 8-bit memory manipulation instruction. reset signal generation clears te0 and teh0 registers to 00h. 4. 6. 3. 8 timer output enable register 0 (toe0) (page 124) incorrect: the toe0 register is used to enable or disable timer output of each channel. channel n for which timer output has been enabled becomes unable to rewrite the value of the to0n bit of timer output register 0 (to0) described later by software, and the value reflecting the setting of the timer output func tion through the count oper ation is output from the timer output pin (to0n). the toe0 register can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. 5. 6. 4. 2 basic rules of 8-bit timer operation function (only channels 1 and 3) (page 132) old: the 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels. this function can only be used for channels 1 and 3, and there are several rules for using it. the basic rules for this function are as follows: (omitted) (7) the lower 8 bits operate according to the settings of tmr0nh and tmr0nl registers. the following four functions support operation of the lower 8 bits: ? interval timer function ? external event counter function ? delay count function ? pwm output correct: the te0 and teh0 registers are used to enable or stop the timer operation of each channel. each bit of the te0 and teh0 registers corresp ond to each bit of the timer channel start register 0 (ts0, tsh0) and the timer channel stop register 0 (tt0, tth0). when a bit of the ts0 and tsh0 registers is set to 1, the correspon ding bit of te0 and teh0 is set to 1. when a bit of the tt0 and tth0 registers is set to 1, the corresponding bit of te0 and teh0 is cleared to 0. the te0 and teh0 registers can be read by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears te0 and teh0 registers to 00h. correct: the toe0 register is used to enable or disable timer output of each channel. channel n for which timer output has been enabled becomes unable to rewrite the value of the to0n bit of timer output register 0 (to0) described later by software, and the value reflecting the setting of the timer output func tion through the count oper ation is output from the timer output pin (to0n). the toe0 register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. new: the 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels. this function can only be used for channels 1 and 3, and there are several rules for using it. the basic rules for this function are as follows: (omitted) (7) the lower 8 bits operate according to the settings of tmr0nh and tmr0nl registers. the lower 8-bit timer supports the following functions: ? interval timer ? square wave output ? external event counter ? delay counter ? pwm output function ? multiple pwm output function (16-pin products only)
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 8 of 13 6. figure 10-13. conversion operat ion of a/d converter (page 235) incorrect: figure 10-13. conversion operation of a/d converter 1 is written to adcs adcs sampling time conversion start time a/d converter operation conversion standby sampling conversion start a/d conversion conversion standby conversion result conversion result undefined sar adcrh int ad conversion time a/d conversion is performed once when the bit 7 (adcs) of the a/d converter mode register 0 (adm0) is set to 1 by software. reset signal generation clears the a/d conversi on result register (adcrl, adcrh) to 00h. correct: figure 10-12. conversion operation of a/d converter 1 is written to adcs adcs sampling time a/d converter operation conversion standby sampling a/d conversion conversion standby conversion result conversion result undefined sar adcrh, adcrl int ad conversion time a/d conversion is performed once when t he bit 7 (adcs) of the a/d converter mode register 0 (adm0) is set to 1 by software. the adcs bit is automatically cleared to 0 after a/d conversion ends. reset signal generation clears the a/d conversi on result register (adcrh, adcrl) to 00h.
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 9 of 13 7. 10. 9. 3 conflicting operations (page 242) old: 10.9.3 conflicting operations writing to the adm0 register has priority if conflict between writing to the adcrh or adcrl register and writing 0 to the a/d conver ter mode register 0 (adm0) occurs at the end of conversion. writing to the adcrh or ad crl register is not performed, nor is the conversion end interrupt signal (intad) generated. new: 10.9.3 conflicting operations <1> reading from the adcrh or adcrl regist er has priority if conflict between writing to the a/d conversion result register (adcrh, adcrl) and reading from adcrh or adcrl register by software operation occu rs at the end of conversion. after the read operation, the new conversion result is written to the adcrh or adcrh register. <2> writing to the adm0 register has priori ty if conflict between writing to the adcrh or adcrl register and writing to the a/d converter mode register 0 (adm0) occurs at the end of conversion. writing to the adcrh or adcrl register is not performed, nor is the a/d conversion end in terrupt signal (intad) generated.
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 10 of 13 8. 24. 3. 1 pin characteristics (page 556) this shows the specificat ions changed in the electrical specifications of 10-pin products. the electrical specifications of ?flash rom: 4 kb of 10-pin products and 16-pin products? will be made for the next revision of the user?s manual: hardware. old: 24.3.1 pin characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit output current, high note 1 i oh1 p00, p01, p02 to p04, p40 per pin -10.0 note 2 ma p40 total note 3 4.0 v ? v dd ? 5.5 v -10.0 ma 2.7 v ? v dd ? 4.0 v -2.0 ma 2.0 v ? v dd ? 2.7 v -1.5 ma p00, p01, p02 to p04 total note 3 4.0 v ? v dd ? 5.5 v -50.0 ma 2.7 v ? v dd ? 4.0 v -10.0 ma 2.0 v ? v dd ? 2.7 v -7.5 ma total of all pins note 3 -60.0 ma output current, low note 4 i ol1 p00 to p04, p40 per pin 20.0 note 2 ma p40 total note 3 4.0 v ? v dd ? 5.5 v 20.0 ma 2.7 v ? v dd ? 4.0 v 3.0 ma 2.0 v ? v dd ? 2.7 v 0.6 ma p00 to p04 total note 3 4.0 v ? v dd ? 5.5 v 80.0 ma 2.7 v ? v dd ? 4.0 v 12.0 ma 2.0 v ? v dd ? 2.7 v 2.4 ma total of all pins note 3 100.0 ma (omitted) new: 24.3.1 pin characteristics (t a = ? 40 to +85 ? c, 2.0 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for 10-pin products: p00 to p04, p40 16-pin products: p00 to p07, p40, p41 -10.0 note 2 ma total of 10-pin products: p40 16-pin products: p40, p41 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v -20.0 ma 2.7 v ? v dd ? 4.0 v -4.0 ma 2.0 v ? v dd ? 2.7 v -3.0 ma total of 10-pin products: p00 to p04 16-pin products: p00 to p07 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v -60.0 ma 2.7 v ? v dd ? 4.0 v -12.0 ma 2.0 v ? v dd ? 2.7 v -9.0 ma total of all pins (when duty ? 70% note 3 ) -80.0 ma output current, low note 4 i ol1 per pin for 10-pin products: p00 to p04, p40 16-pin products: p00 to p07, p40, p41 20.0 note 2 ma total of 10-pin products: p40 16-pin products: p40, p41 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v 40.0 ma 2.7 v ? v dd ? 4.0 v 6.0 ma 2.0 v ? v dd ? 2.7 v 1.2 ma total of 10-pin products: p00 to p04 16-pin products: p00 to p07 (when duty ? 70% note 3 ) 4.0 v ? v dd ? 5.5 v 80.0 ma 2.7 v ? v dd ? 4.0 v 12.0 ma 2.0 v ? v dd ? 2.7 v 2.4 ma total of all pins (when duty ? 70% note 3 ) 120.0 ma (omitted)
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 11 of 13 9. 24. 6. 1 a/d converter characteristics (page 567) this shows the specificat ions changed in the electrical specifications of 10-pin products. the electrical specifications of ?flash rom: 4 kb of 10-pin products and 16-pin products? will be made for the next revision of the user?s manual: hardware. old: 24.6.1 a/d converter characteristics (target ani pin : ani0 to ani3) (t a = ? 40 to +85 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution v dd = 5 v ?1.7 ?3.1 note 2 lsb v dd = 3 v ?2.3 ?4.5 note 2 lsb conversion time t conv 10-bit resolution 2.7 v ? v dd ? 5.5 v 3.4 18.4 s ? 2.4 v ? v dd ? 5.5 v 4.6 18.4 s ? zero-scale error note 1 e zs 10-bit resolution v dd = 5 v ?0.19 note 2 %fsr v dd = 3 v ?0.39 note 2 %fsr full-scale error note 1 e fs 10-bit resolution v dd = 5 v ?0.29 note 2 %fsr v dd = 3 v ?0.42 note 2 %fsr integral linearity error note 1 ile 10-bit resolution v dd = 5 v ?1.8 note 2 lsb v dd = 3 v ?1.7 note 2 lsb differential linearity error note 1 dle 10-bit resolution v dd = 5 v ?1.4 note 2 lsb v dd = 3 v ?1.5 note 2 lsb analog input voltage v ain 0 v dd v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this is the characteristic evaluation valu e plus or minus 3. these values are not used in the shipping inspection. new: 24.6.1 a/d converter characteristics (target pin: ani0 to ani6, internal reference voltage) (t a = ? 40 to +85 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error notes 1, 2, 3 ainl 10-bit resolution v dd = 5 v ? 1.7 ?3.1 lsb v dd = 3 v ? 2.3 ?4.5 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani6 2.7 v ? v dd ? 5.5 v 3.4 18.4 s ? 2.4 v ? v dd ? 5.5 v note 5 4.6 18.4 s ? 10-bit resolution target pin: internal reference voltage note 6 2.4 v ? v dd ? 5.5 v 4.6 18.4 s ? zero-scale error notes 1, 2, 3, 4 e zs 10-bit resolution v dd = 5 v ? 0.19 %fsr v dd = 3 v ? 0.39 %fsr full-scale error notes 1, 2, 3, 4 e fs 10-bit resolution v dd = 5 v ? 0.29 %fsr v dd = 3 v ? 0.42 %fsr integral linearity error notes 1, 2, 3 ile 10-bit resolution v dd = 5 v ? 1.8 lsb v dd = 3 v ? 1.7 lsb differential linearity error notes 1, 2, 3 dle 10-bit resolution v dd = 5 v ? 1.4 lsb v dd = 3 v ? 1.5 lsb analog input voltage v ain target pin: ani0 to ani6 0 v dd v target pin: internal reference voltage note 6 v reg note 7 v ( notes are listed on the next page.)
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 12 of 13 notes 1. typ. value is the average value at t a = 25 ? c. max. value is the average value ? 3 at normal distribution. 2. these values are the results of characte ristic evaluation and are not checked for shipment. 3. excludes quantization error ( ? 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. 5. set the lv0 bit in the a/d converter mode register 0 (adm0) to 0 when conversion is done in the operating voltage range of 2.4 v v dd < 2.7 v. 6. set the lv0 bit in the a/d converter mode register 0 (adm0) to 0 when the internal reference voltage is selected as the target for conversion. 7. refer to 24.6.3 internal reference voltage characteristics . cautions 1. arrange wiring and insert the capacitor so that no noise appears on the power supply/ground line. 2. do not allow any pulses that rapidly change such as digital signals to be input/output to/from the pins adjacent to the conversion pin during a/d conversion. 3. note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for a/d conversion.
renesas technical update tn-rl*-a023a/e date: feb. 6,2014 (c) 2014. renesas electronics corporation. all rights reserved. page 13 of 13 10. 24. 6. 4 data retention power supply voltage characteristics (page 568) this shows the specificat ions changed in the electrical specifications of 10-pin products. the electrical specifications of ?flash rom: 4 kb of 10-pin products and 16-pin products? will be made for the next revision of the user?s manual: hardware. old: 24.6.4 data retention power supply voltage characteristics (t a = ? 40 to +85 ? c, vss = 0 v) parameter symbol conditions min. typ. max. unit data retention power supply voltage range v dddr 1.9 5.5 v caution data is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage range. note that data in the ram and resf registers might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage range. new: 24.6.6 data retention power supply voltage characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.9 5.5 v caution data in the resf register is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage (v dddr ). note that data in the resf register might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage (v dddr ). normal operation spor reset period normal operation (data retention mode) v dd v dddr rising of v spor falling of v spor

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